资源列表
run
- verilog HDL PARTAN 3E100的流水灯程序-verilog HDL PARTAN 3E100 water light program
cntrlr
- verilog code for bus controller
atm_cell
- verilog code for atm_ce-verilog code for atm_cell
alarm
- vhdl alarm design code-vhdl alarm design code
syncram
- verilog rtl and testbench code for single port sync ram
project
- VHDL编写的ATM代码,能实现全部的功能，经过了测试和仿真。-VHDL code written in ATM, can realize all the functions, after the test and simulation.
bahe
- 采用verilog设计的拔河比赛，在QuartusII9。0仿真验证并在DE2上测试过-Using Verilog to design the tug of war, in QuartusII9. 0 simulation and test on DE2
20_lcd
- 一种基于verilog和quartusII的液晶显示驱动的封装，LCD（12864）封装。-Verilog and quartusII based LCD display driver package, LCD (12864) package.
number_mod
- 以verilog设计最大为99数字在2个数码管资源上的显示，采取的方法是同步动态扫描。-Verilog design to a maximum of 99 digits displayed on two digital resources, the approach is synchronous dynamic scanning.
buzzer_sos_2
- 用verilog产生“SOS信号”，就是有次序的控制输出莫斯密码的“点”，“画”和“间隔”。一个比较好玩的源码。-Produce " SOS signal" with verilog, is to have control of the output sequence Moss password " point" , " painting" and " interval." A more fun source.
run_flash_led
- 用verilog建立一个并行操作的流水灯模块。扫描频配置定为100 Hz，而每一个功能模块在特定的时间内，将输出拉高。-The establishment of a parallel operation of light water module verilog. Scanning frequency configured as 100 Hz, and each functional module within the specified time, the output high.
vga
- 用verilog设计控制程序从 ROM模块读取图片信息，然后写入 VGA接口。控制程序每隔250ms写入不同的信息至VGA接口，在屏幕上会出现小绿人的动画。-Reading the image information from the ROM module verilog design control procedures, and then write the VGA connector. Control program every 250ms write different messages