资源列表
6f041ed721eb
- 简单的dsp与fpga接口代码。emif-Dsp and fpga simple interface code. emif
CORDIC
- pipelined CORDIC in structural model that contains 16 stages
simplefft
- simplified fft implemented in verilog for 8 points
run time expandable cache
- Expandable cache proposed by Bournoutian and Orailoglu is very efficient in reducing miss rate and energy consumption with small area overhead. However, the original expandable cache with only one expansion scheme may lead to thrashing problems. In t
DM9000A
- 用Verilog语言实现fpga对dm9000a的驱动-Achieve fpga for driving with Verilog language dm9000a
bit_synchronize
- fpga开发的位同步处理模块，能够实现功能并实现良好的效果-fpga developed bit synchronization processing module to achieve the function and achieve good results
calc_16_01_14
- A VHDL code for a simple calculator.It reads the operator and operands form the memory and execute
adder
- A VHDL code for adding two numbers.It takes two 8bit words and give sum as output.
alu
- A vhdl code for CPU unit with pipeling.It performs all basic operations like ADD,SUB,Shift
miracle
- to implement the vhdl code for bacic ckts
New-Folder
- to learn bout development of vhdl code
New-Folder
- to learn about some vhdl coding