资源列表
vhtoverilog
- A major obstacle of thge code is to convert verilog to convert an vhdl code that stands in the way of efficient test response compaction are the unknown values (x-values) captured by scan cells during testing. If test responses with x-values ar
vhdl-all-english
- A major obstacle that stands in the way of efficient test response compaction are the unknown values (x-values) captured by scan cells during testing. If test responses with s and the correctness of the compactor inputs cannot be verified at
src
- VGA条形图案的显示，用verilog写的-this Source code is about the display of Stripe pattern
src1
- 关于串口通信的一段源代码， 希望能有帮助-this source code is about Serial communication
led_flow
- verilog 控制灯的闪烁，运用状态机写的-this code is about the Flicker of light
zifu
- 关于用vga显示字符的一段程序，verilog-this code is about the display of Character
Double_FPU.PDF
- floating point unit code it is very usefull for development of floating point units
tringular
- triangular wave in VHDL
lcd_verilog
- lcd programming for FPGA
7_seg
- seven segment interfacing.
arm
- 此程序是ARM+FPGA的总线通信程序，我只提供FPGA这一边的，其实我现在把这个程序移植到dsp+cpld上面去了，那个程序其实都出不多-This program is ARM+ FPGA bus communication procedures, I only FPGA side, in fact, I now put this program ported to dsp+ cpld go above, and that the program actually much
miaobiao
- 在EPM240上实现秒表功能，4个数码管显示-Stopwatch function on EPM240, 4 digital display