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  1. ALU-and-Register-File

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  2. ALU&Register Files(RF)之實現和其資料路徑的組合,包含了(1)ALU(2)Register File (RF)(3)Serial-in parallel-out register file(4)ALU + RF datapath-To learn the Verilog design for ALU and Register Files which are two main building blocks of a CPU.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-28
    • 文件大小:6.46kb
    • 提供者:sara kuo
  1. Tri-Eth

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  2. 采用xilinx三太以太网ip核,tri-mode MAC完成千兆以太网数据传输-Too Ethernet using xilinx ip three nuclear, tri-mode MAC Gigabit Ethernet data transmission is completed
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-18
    • 文件大小:4.6mb
    • 提供者:望天
  1. Finite-State-Machines

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  2. 此壓縮檔包含四個資料夾(1)Moore Machine(2)Mealy Machine(3)Memory(4)A mini system,學習如何以階層化的方法去撰寫系統內部的小工作區塊,並了解迷你CPU內部的記憶體簡單的運作情形&資料串流-design the finite state machine and the mini system.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-05
    • 文件大小:9.51kb
    • 提供者:sara kuo
  1. MIPS32

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  2. 此資料夾為實現一單一時脈週期MIPS32處理器架構源碼,包含了控制單元、資料記憶體、資料路徑、指令記憶體四個部分,以程式碼: (共10個)  instruction_mem.v、data_mem.v  control.v、alu_control.v  program_counter.v、reg_file.v  alu_32bit.v、adder_32.v、sign_extend.v來實現。-MIPS (originally
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-06
    • 文件大小:3.82kb
    • 提供者:sara kuo
  1. eetop.cn_fft

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  2. Hello, i have uploaded some interesting files - Hello, i have uploaded some interesting files ...
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-28
    • 文件大小:155.92kb
    • 提供者:viet
  1. 16FFTverilog

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  2. Hello, i have uploaded some interesting files - Hello, i have uploaded some interesting files ...
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-13
    • 文件大小:2.41kb
    • 提供者:viet
  1. cam_generic_8s

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  2. verilog 开发实例 无线通 信网络-verilog examples of the development of wireless communication networks
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-04
    • 文件大小:3.43kb
    • 提供者:鹧鸪天
  1. myfir

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  2. VHDL设计的FIR滤波器,有Matlab设计文件,Quartus II工程以及Modelsim仿真结果和说明文件-VHDL design FIR filters, Matlab design documents, Quartus II project and Modelsim simulation results and documentation
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-12
    • 文件大小:2.73mb
    • 提供者:fangying
  1. hierarchical-code

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  2. Abstract—This paper presents a highly effective compactor architecture for processing test responses with a high percentage of x-values. The key component is a hierarchical configurable masking register, which allows the compactor to dynamically ad
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-13
    • 文件大小:2.47kb
    • 提供者:shankar.m
  1. handbook

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  2. Abstract—This paper presents a Viterbi-based test compression algorithm/architecture that provides high encoding efficiency and scalability with respect to the number of test channels. The proposed scheme finds a set of compressed test vectors
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-16
    • 文件大小:3.65mb
    • 提供者:shankar.m
  1. upload

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  2. A major obstacle that stands in the way of efficient test response compaction are the unknown values (x-values) captured by scan cells during testing. If test responses with x-values are compacted, some of the outputs of the compactor may als
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-24
    • 文件大小:32.98kb
    • 提供者:shankar.m
  1. source

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  2. A major obstacle that stands in the way of efficient test response compaction are the unknown values (x-values) captured by scan cells during testing. If test responses with x-values are compacted, some of the outputs of the compactor may als
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-24
    • 文件大小:10.48kb
    • 提供者:shankar.m
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