资源列表
verilog_CPU
- 用verilog写的RISC_CPU，描述文件很详尽，含有测试文件-Written by verilog RISC_CPU, very detailed descr iption of the file containing the test file
vhdl
- 这是一些经典的vhdL源代码，这些代码，用于嵌入式学习，对于想学vhdL的同学很有帮助-This is some classic vhdL source code, the code, for embedded study, is very helpful for students want to learn the vhdL
code
- ADPCM解码器,4位adpcm音频数据解压缩成16位的pcm数据，采样频率为20KHz.-ADPCM decoder
1024fft
- verilog编写的1024点的fft快速傅里叶变换代码-verilog prepared 1024 point fft Fast Fourier Transform code
des_vhdl_code
- decription aes using vhdl code
dec_aes
- decription aes vhdl code for fpga
8051_cpu_verilog
- The 8051 microcontroller is member of MCS-51 family, originally designed in the 1980 s by Intel. The 8051 has gained great popularity since its introduction and is estimated it is used in a large percentage of all embedded system products. The basic
C_ADDSUB_V1_0
- 针对xilinx器件的重要库文件，能够加快基于xilinx器件的工程开发，提高系统的性能。-For important library xilinx devices, to accelerate project development based on xilinx devices to improve system performance.
C_COMPARE_V1_0
- 针对Xilinx器件的关键库文件，该库文件实现了比较器的功能，能够加快项目的进度！-The key database file for Xilinx devices, the library implements the comparator function, to expedite the progress of the project!
aes_-vhdl
- aes encription coding in vhdl language
AES128
- AES128 encription vhdl code
t3_sdram
- 完成sdram读写操作，并附有测试脚本文件，已通过后仿验证。该程序主要包括上电初始化模块，刷新模块，读、写模块等，并采用FSM控制所有模块，完成数据的读写操作-Sdram read and write operations to complete, with a test scr ipt file has been verified through simulation. The program includes power-on initialization module, refresh m