资源列表
synver
- Synopsis Verilog HDL
Verilog_HDL_Reference_Manual
- Altera DE2 board manual
alarm
- This program is used to display the alarm time.
MAC
- this a Multiplier and Accumulate (MAC). written in VHDL-this is a Multiplier and Accumulate (MAC). written in VHDL
48_order-FIR-filter-with-8-folder
- 该代码是设计一个48阶FIR滤波器的文档，该设计方案主要运用了数字信号处理VLSI实现中的折叠的方式。-The code is a 48-order FIR filter design document, the main use of the design of VLSI implementation of digital signal processing in the way of folding.
H1602B_2
- 1602verilog 显示字符，one world one dream-1602verilog englishword，one world one dream
Beep-Music
- VHDL 蜂鸣器音乐程序——两只老虎，包含 官方模块调用实例。-VHDL the Buzzer music program- two tigers, including the official calling module instance.
Adc
- FPGA(xilinx可编程芯片)试验箱 实验程序1 模拟/数字转换ADC- FPGA(xilinx)test bos program1 ADC
MonitorB
- 用VHDL写的一个信息监视系统，包括对信息的整形、串并转换和奇偶校验等 还有状态的判断，信息格式的判断等 一个监视器-VHDL write a monitoring system, including the shaping of information, serial-to-parallel conversion and parity status judgment, the judgment of the information format monitor
MODELSIM
- MODELSIM的经典教程，可以快速学会MODELSIM的一些基础应用-MODELSIM classic course, can quickly learn to MODELSIM application of some basic
MODELSIM
- Modelsim 经典教程，推荐大家看下-Modelsim Tutorial classic recommend you facie