资源列表
yuying
- 一个用 MAX puls编写的 语音存储程序，可以直接使用-A speech written by MAX puls stored procedures, you can directly use ~ ~
EDAVHDL实验指导书
- EDAVHDL实验指导书， 《EDA(VHDL)课程设计》指导书详解 - EDA(VHDL)课程设计，指导书 。
LCD1602-display
- verilog编程实现在lcd1602上显示字符，在学习板上验证-verilog programming shown on the lcd1602 character, learning board verification
SHIFT4_Parallel-input-serial-output
- 4位串行输入并行输出移位寄存器和移位寄存器产生伪随机序列的源代码以及相关分析-Four serial input and parallel output shift register and shift register of the source code of pseudo-random sequence and correlation analysis
基于FPGA的李沙育图形发生器
- 这是一个用MAX+PLUSII开发FPGA（1K30器件）开发的李沙育图形发生器（硬件描述语言部分）。-This is a development with MAX PLUSII FPGA (1K30 device) developed Lissajous Pattern Generator (hardware descr iption language).
timer
- 这是一个基于FPGA设计的24时多功能数字钟，具有正常星期、时、分、秒计时，动态显示，保持、清零、快速校分、整点报时、闹钟功能。-This is an FPGA-based design of multi-function digital clock 24 hours, with a normal week, hours, minutes, seconds, timing, dynamic display, maintaining, resetting, fast school hours, t
WishboneSpecification
- WISHBONE Bus specification
EDA2
- 比较器和DA器件实现AD功能的电路设计以及在EDA试验箱上的具体操作-Comparator and DA function devices to achieve AD EDA circuit design and the specific operation on the chamber
Cronometro
- time counter with a display output
EDA_dianzhen
- 使用verilog语言写的16*16的点阵，能够实现左移、右移、暂停、复位等功能，可以自己定制RAM，改变显示的内容。-Verilog language written using the 16* 16 dot matrix, to achieve left, right, pause, reset and other functions, you can customize RAM, change the display content.
12864PVHDL
- 主要是基于VHDL的12864的液晶显示的程序啊！-Mainly based on the 12864 LCD VHDL program ah!
fred
- FPGA等精度测量 程序，已仿真通过。-FPGA and precision measuring program, already through simulation.