资源列表
ethmac10g verilog代码
- 10G eth mac verilog代码参考下载
sync_fifo
- 这个实现了一个异步的fifo ,通过同步的方法把异步fifo变为同步的fifo来实现，简化了硬件实现的工程-This implements an asynchronous fifo, by synchronizing the asynchronous method into a synchronous fifo fifo to achieve, simplifying the hardware implementation of the project
verilog
- vhdl学习资料 清华大学信息学院课件 绝对值得下载-Tsinghua University, studying information vhdl Institute information is worth courseware download
DE2_labs_verilog
- Quartus 14.1 download
qam16
- 实现16进制的QAM调制， 编译通过-Achieve 16 to 229 QAM modulation, achieve 16 to 229 QAM modulation, compiled by
DE2_labs_verilog
- This the code writing on verilog-This is the code writing on verilog
lcd12864--zhongjiban
- 这是本人的一个小练习，简单的实现了LCD12864的初始化，清零，数据显示及开关控制。已仿真通过。请参考。-this is a personal practice of LCD12864,it simply accompolishes some functions.
digtal_clock
- C51单片机上，显示时钟，闹钟，计时，用Xilinx ISE Design 编写-C51 microcontroller, clock, alarm clock, time, prepared with Xilinx ISE Design
timecounter60sandpause
- 计时器数码管做到60s计数，外接键盘按键暂停-Digital timer 60s do count, an external keyboard to pause
Project-8
- 课程设计时用verilogHDL写的MIPS CPU-MIPS CPU coded with Verilog HDL
Design-of-Optimized-Reversible-BCD-Adder-Subtract
- Design of Optimized Reversible BCD Adder-Subtractor 229
UAET_323_to_flow_led
- VHDL 实现串口收发并点亮流水灯，仿真成功(VHDL realizes serial port transceiver and lighting water lamp)