资源列表
shuzipaobiao
- 在ISE环境下用Verilog HDL写的一个简易的数字跑表，最大量程为60分钟，精确到毫秒级，有复位键和暂停键。-In the ISE environment, using Verilog HDL to write a simple digital stopwatch, the maximum range is 60 minutes, accurate to the millisecond, the reset button and pause button.
DM9000A
- 用Verilog语言实现fpga对dm9000a的驱动-Achieve fpga for driving with Verilog language dm9000a
lcd
- 实现ICD显示，在ISE8.2运行，芯片为xinlix的virtex4-To achieve ICD display, run in ISE8.2 chip xinlix the virtex4
calculator
- VDHL实现2*8的按键扫描和100以内的+、-、*运算-VDHL realize 2* 8 buttons scanning and 100+,-,*within.
youhua-Qsys-system-performance
- FPGA的Qsys系统的设计的优化设计中文资料-Qsys system optimization design of FPGA design Chinese data
VHDL_Syntax
- 这是一本关于VHDL编程语言语法的电子书，里面介绍了VHDL的语法。-This is about a programming language VHDL grammar books, which introduce the VHDL syntax.
Myszz
- 基于EDA的用VerlogHDL编写的多功能数字闹钟-EDA' s written by VerlogHDL based multifunction digital alarm clock
CoDeSys-programming-Introduction
- codesys编程简介，CoDeSys 是一种功能强大的PLC软件编程工具，它支持IEC61131-3标准IL 、ST、 FBD 、LD、 CFC、 SFC 六种PLC编程语言，用户可以在同一项目中选择不同的语言编辑子程序，功能模块等。-CoDeSys programming Introduction
串口通信
- 该程序主要实现FPGA串口通信，包含源码和串口调试工具(The program mainly to achieve FPGA serial communication, including source code and serial debugging tools)
Single_cpu
- 单周期CPU自己课程大作业做的，亲测好用，verilog语言，适用vivado(Single cycle CPU course to do, pro - use, Verilog language, suitable for vivado)
6.An-FPGA-Based-High-Speed-IEEE-754-Double-Precis
- An FPGA Based High Speed IEEE-754 Double Precision Floating Point Multiplier
Memory
- Single Clock Synchronous RAM Design Example with Quartus-Single Clock Synchronous RAM Design Example with QuartusII