资源列表
rs_5_3_gf256_latest.tar
- this paper deal with rs decoder algorithm-this paper deal with rs decoder algorithm
rs_5_3_gf256_latest.tar
- VHDL传资料的详细功能、包含内容说明(至少要20个字)。尽量不要让站长把时间都-VHDL
AlteraSdramIP
- Altera Sdram IP 源码，VHDL写的
8b10encode
- 8b10b编码器是设计高速数据发送的重要编码方式，其中有源代码还有具体设计文档-8b10b encoder design of high-speed data transmission encoding, including source code, there are specific design documents
lcd
- Verilog初学者实验程序。已在quartus下测试成功。-Verilog beginners experimental procedures. Been in quartus under test success.
traffic_light
- 基于VHDL的FPGA交通灯设计源码，可以实现交通灯信号变化的控制-VHDL for FPGA-based design of traffic light source, can achieve the control of traffic light signal change
design
- 计算机组成原理课程设计报告 微程序控制计算机设计-Principles of Computer Organization course design report Micro-program control computer design
i2c_protocol_Chinese
- 完整的I2C协议，中文版的，可以帮助了解I2C实现的整个过程-Complete I2C protocol can help us understand the whole process of achieving I2C
mc8051_design
- This is version 1.4 of the MC8051 IP core.
XAPP868
- E1/T1时钟提取和恢复源码 是xilinx的IP源码-E1/T1 clock recover code,it is xilinx s IP code
geleima--10
- 格雷码计数器 vhdL实现 quartus编译通过-Gray code counter VHDL quartus compiled by
dds
- dds数字信号发生器，实现1/4rom存储，正弦，余弦，三角波，锯齿波产生，AM调制-the dds digital signal generator, achieve 1/4rom store, generate sine, cosine, triangle wave, sawtooth, AM modulation