资源列表
rtc
- real time clock using spartan3e fpga
Dac
- FPGA(xilinx) 赛灵思试验箱 试验程序2 数字/模拟转换DAC FPGA(xilinx) testbox test programe DAC-FPGA(xilinx) testbox test programe DAC
tests
- test circuit about VHDL 测试程序 可运行-test circuit about VHDL test program can be run
jiaotongligh
- 设计的交通灯应用在两条主干道的汇合点形成十字交叉路口，为确保车辆安全，迅速地通行，在交叉道口的每个入口设置了红，绿，黄三色信号灯。红灯亮禁止通行，绿灯亮允许通行，黄灯亮则警告行驶中的车辆，并让它们有时间停靠到禁行线之外。--Design used in traffic lights the confluence of two main roads cross the intersection form, in order to ensure their safe and prompt acces
ethernet.tar
- verilog写的以太网硬件模型，使用xilinx FPGA，ieee802.3ae-an ethernet model in Verilog，using a Xilinx FPGA，and the function：IEEE 802.3ae Media Access Control (MAC) Parameters, Physical Layers, and Management Parameters for 10 Gb/s Operation
PQtor
- PQCM和FPGA空间应用分子污染监测仪设计PQCM FPGA -PQCM and FPGA space design of molecular contamination monitor
mendianlu
- 用VHDL语言描述了各种门电路，与门，或门，非门，与非，或非-VHDL language describes the various gates, AND gates, OR gates, NAND, NAND, NOR, etc.
ldpc_decoder_802_3an
- 802.3an ldpc码编码、译码设计，使用VERILOG hdl语言编写，包括测试代码，
div_n_0_5
- 使用verilog实现任意奇数n+0.5分频，使用ise11.1和modelsim se6.5仿真测试-Using an arbitrary odd number n+0.5 verilog divide, the use of simulation testing ise11.1 and modelsim se6.5
CPLDUART
- 文件列表
ethmac10g_latest.tar
- 10G高速以太网mac VERILOG源码 可仿真可实现-10G high speed Ethernet MAC verilog code can be used for synthesis or inplementation
ethmac10g_latest.tar
- ethmac10g_latest是用verilog编写的10gbps的以太网mac，对工程开发非常有用！-ethmac10g_latest is written in verilog 10gbps Ethernet mac, very useful for the development of the project!