资源列表
fpga2
- an artical about controller area protocol and fpga device that i found on the net.
bcdseg7
- bcd码的七段数码管显示vhdl程序 bcd码的七段数码管显示vhdl程序-bcd-yard seven-segment LED display vhdl program bcd-yard seven-segment LED display vhdl program
clock
- 有时分秒显示，定时功能，24小时12小时转换的时钟vhdl编写-Sometimes, minutes and seconds display, timing function, a 24-hour clock 12-hour conversion write vhdl
counter
- vhdl编写计数器，打开可用，有进位 vhdl编写计数器，打开可用，有进位-vhdl preparation counter, open the can, there are binary vhdl preparation counter, open the can, there are binary
DDS
- vhdl编写的dds信号发生器 这是比较古老的写法，但很简单-vhdl prepared dds signal generator which is a more ancient writing, but it is simple
CycloneII_NiosII_2C35_Rev02_DB_SCH
- nios开发板电路图CycloneII_NiosII_2C35_Rev02_DB_SCH.zip-nios development board circuit CycloneII_NiosII_2C35_Rev02_DB_SCH.zip
decoder38
- vhdl编写的38译码器 完全文件，打开可用-vhdl decoder written 38 full document, open the can
gate
- vhdl编写的逻辑门电路程序，适合初学者，很简单-vhdl programs written in the logic gate circuit suitable for beginners, very simple
key_led
- 简易计算器的键盘和LED显示，很简单，但也可以说很复杂-Simple calculator keyboard and LED display, very simple, but can also be said very complicated
counter_8050
- 本实验的功能为：10进制从80-50的计数器，2次/秒，这里的clk为50MHZ,一秒一次需要外加分频功能-The function of this experiment as follows: 10 binary counters from 80-50, 2 times/sec, where clk is 50MHZ, second function of a need for external divider
waterled_2group
- LED0--LED11,由LED0 LED1开始循环亮，2个灯为一组，每1秒换一组灯亮，这里用的时钟为50MHZ，因此需要外加一个分频器进行分频- LED0- LED11, from the beginning of the loop LED0 LED1 light, two lights as a group, every 1 second for a group of lights, where the clock used for 50MHZ, plus a divider so the
waterled
- LED3--LED10,由LED10开始循环亮，每1换个灯亮，按SW1就停止跳动，再按一下就继续再跳动-LED3- LED10, from the beginning of the loop LED10 bright lights for every one from another, according to SW1 to stop beating, and then click on the continue beating again