资源列表
BCD
- 利用Verilog HDL语言实现BCD码的加法-Using Verilog HDL language implementation of BCD addition
TWO
- 利用Verilog HDL语言实现公共表达式交叉系数滤波器-Using Verilog HDL language implementation public expression cross coefficient filter
cpu_cache_interrupt
- verilog写的CPU 五级流水 带cache 中断-the the CPU five water with verilog to write cache interrupt
chenxu
- Verilog HDL 16选一数据选择器-Verilog HDL 16 election of a data selector
clock
- 一个简单的数字时钟Verilog仿真程序，60秒1分钟，60分一小时，24小时一天，265天一年。代码逻辑简化不含状态机，易理解。附激励文件可直接仿真。-A simple digital clock Verilog simulation program 60 seconds, 1 minute, 60 hours, 24 hours a day, 265 days a year. The code logic simplifies excluding state machine, easy to
chenxu
- 利用状态机设计正弦波信号发生器： //输出4位接4位的DA转换，即4位数字信号输出可直接通过DA转换为模拟信号。 -The use of state machine design is the sine wave signal generator:// output 4 connects a 4-bit DA converter, i.e. the 4-bit digital signal output can be directly through the DA converte
chengxu
- 设计状态机从SRAM中读取数据，并相加，即求SRAM【7：0】【2：0】中8个字节数的和并输出，SRAM为内置RAM-Design state machine to read data from the SRAM, and added, that is seeking SRAM [7:0] [2:0] 8 bytes and output, SRAM built-in RAM
chengxu
- 读取外部RAM的状态机 RAM接口OE，输出使能 WR，低电平写RAM AB【7：0】地址总线 DB【7：0】地址总线 //将RAM 0至127的数据读出并相加最后的结果存入地址254（低8位）255（高8位） -State machine reads the external RAM RAM interface OE Output Enable WR, low-level to write RAM AB [7:0] address bus DB [7:0
text_fir_lbq
- 本人毕业论文中的一个模块，我FIR有限长滤波器，可以直接编译仿真下载。。实际测试可用-A module in my thesis, I finite length FIR filters can be directly compiled simulation download. . The actual test are available. .
weitebi_notes
- 维特比译码 ，说明比较详细， 用于卷积的译码，很不错-Viterbi decoding, a more detailed descr iption
shuzishizong
- 通过按键实现数字时钟的时间调节和 闹钟调节 -Digital clock alarm clock is adjustable
jiaotongdeng
- 状态机实现十字路口的交通灯红黄绿 代码中用八位的led高三位灯分别表示a路口的红黄绿低三位表示b路口的红黄绿-State machine to achieve the crossroads of traffic lights red yellow and green code with eight high three LED lights denote a junction of red, yellow, and green the lower three b junction of red