资源列表
Xilinx-Timing
- Xilinx FPGA 时序约束资料，原厂出品，经典不需要理由-Xilinx FPGA timing constraint information, original, classic no reason
shixusuccessful
- 利用VHDL语言，对时分复用通信系统的仿真实现，包括序列产生到序列接收等部分。-Simulation time division multiplexing communication system
DCO_ST
- 单相数字锁相环 鉴相器 环路滤波器 数控振荡器-Single-phase digital phase-locked loop phase detector loop filter numerically controlled oscillator
MDIO
- 网络PHY88E1111的 寄存器 通讯协议的 verilog描述 能实现 lookback 能读出PHY的资料-The register communication protocol Verilog descr iption of the network PHY88E1111 lookback can read the PHY data
DPLL_TEST
- 单相数字锁相环 鉴相器 环路滤波器 数控振荡器-Single-phase digital phase-locked loop phase detector loop filter numerically controlled oscillator
gen_clk
- 占空比可变的信号发生器 解释的好麻烦那 不知道怎么解释-A variable duty cycle signal generator
fpga_GRT
- PWM信号发生器，可进行频率调整带宽30M，可进行占空比调整精度0.02 -PWM signal generator, adjust the frequency bandwidth of 30M, 0.02 of the duty cycle can be adjusted accuracy
Golf_Test
- 用verilog语言实现的高尔夫模拟机下位机检测，参数包括速度、仰角和偏角。-Verilog language golf simulator under-bit machine detection parameters include speed, elevation and declination.
seg7
- 通过Verilog语言，显示七段数码管，在cycloneI上能正确显示-Verilog language, showing seven-segment LED display correctly, cycloneI
EDA
- vhdl语言编写的交通灯。有程序有电路图。-The VHDL language the traffic lights. There is a program to the circuit diagram.
clock-pro
- 一款用verilog 编写在经典时钟程序，很好用，和大家分享了-A verilog prepared in the classic clock program, easy to use, and to share with you! ! !
h_adder
- 半加器VHDL代码，包含所有文件，较清晰-Half adder VHDL code, including all documents, clearer