资源列表
src
- n位二进制绝对值减法器，基于FPGA的硬件语言-n-bit binary absolute value subtraction, FPGA-based hardware language
dtrigger
- 在Quartus软件中用Verilog HDL编写的D触发器的源代码-In the the Quartus software using the Verilog HDL prepared D flip-flop the source code
vclkdiv
- 在QuartusII软件中用Verilog HDL编写的关于分频器的源代码-With in QuartusII software written in Verilog HDL source code of the divider
ji_shu_qi
- 在QuartusII软件中用Verilog HDL编写的计数器的源代码-Verilog HDL prepared counter with in QuartusII software source code
shift_register
- 在QuartusII软件中用Verilog HDL编写的移位寄存器的源代码-The source code of the shift register in QuartusII software using Verilog HDL prepared
RS_bmq
- 在QuartusII软件中用Verilog HDL编写的RS编码器的源代码-The RS encoder Verilog HDL prepared with in QuartusII software source code
MotorVHDL
- 一个关于松下伺服电机驱动及反馈的VHDL程序-VHDL program a Panasonic servo motor drive and feedback
keshe
- 低通滤波器，基于eda使用vhdl语言实现数字滤波的功能-Low-pass filter, based on the the EDA use VHDL language digital filtering function
test12
- 自己用VerilogHDL语言编写的时钟程序，包括时钟进位计数模块，数码管显示模块和闹钟模块。在cpld芯片上经测试有效（开发环境没找到VerilogHDL，就选了VHDL，其实他们不一样的……）-Clock with Verilog HDL language written procedures, including clock binary counter module, digital display and alarm modules. The CPLD chip has been te
i2c
- I2C总线，已经验证，包括ModelSim文件-I2C bus has been verified, including ModelSim files
20130517
- 采用cpld控制ads8364实现六通道采样，采用verilog语言-Cpld control ads8364 six-channel sampling, using the Verilog language
src
- 12秒定时控制电路: 当12秒定时时间结束时，L1指示灯熄灭，L2指示灯以每秒5次速度闪烁。-12 seconds timing control circuit: When the 12 seconds when the timer expires, the indicator goes off L1 L2 indicator flashes 5 times per second speed.