资源列表
YINYUE
- EDA梁祝音乐，但是其中有一个错误，不知道怎么更改-EDA Butterfly music, but there was an error, do not know how to change
8051-vhdl
- 向比MC8051，C8051的书写更加工整，更加适合处理设计的学习，并且多一个调试单元，绝对震撼!-To than the MC8051, C8051 write more neatly, more suited to deal with the design of the study, and a debug unit, absolutely shocked!
ps2-vhdl
- ps2-vhdl源码 希望对大家有帮助-PS2-VHDL source code we want to help! ! ! !
bluetooth-vhdl
- bluetooth--vhdl源码 仅供参考 希望对大家有帮助-The bluetooth- VHDL source code we want to help! ! !
processor-vhdl
- 包内有dsp320vc33，dsp6211，dsp6415，dsp6713,hc11_core(附加Verilog代码),p89c51,std8980,zr36060的源码-Dsp320vc33 dsp6211 dsp6415, dsp6713 hc11_core (additional Verilog code), P89C51 std8980 ZR36060 the source package
OV7670_
- ov7670是数据手册 对于ov7670的驱动很有帮助-ov7670 ov7670 drive helpful Data Sheet
Mario
- 基于fpga 的小游戏，用键盘控制的，实际可以运行-FPGA-based game control with the keyboard, can actually run
VHDL
- verilog程序包 包括数码管显示 lcd 红外线接收和读取 -Verilog package includes digital display lcd infrared receiver and read
tkzc
- verilog hdl蜂鸣器演奏天空之城-the Verilog HDL buzzer playing Castle in the Sky
PCtoLCD2002
- 单片机字模软件 单片机字模软件-The chip matrix software chip matrix software chip matrix software
clock-generator
- 在集成电路设计中，时钟乃必备元素，但时钟产生器一般为模拟或者数模混合电路，在以数字电路为主的ASIC设计中，一般使用其模型来仿真。 写一个时钟产生器模块。-In integrated circuit design, the clock is an essential element, but the clock generator is generally analog or mixed analog-digital circuits, digital circuits based ASIC
eda1
- 原理图方式实现8位全加器，文件类型为gdf ，vhd 文件-8-bit full adder schematic way, the file type for the GDF vhd file