资源列表
the-taxi-meter
- 利用MAX plus10.2对所设计的出租车计费器的VHDL代码进行仿真，并在FPGA数字实验系统上实现了该控制。-The MAX plus10.2 the design of the taxi meter VHDL code simulation, and FPGA digital experimental system To implement the control. This is the decoding module
shuzipaidui
- 3*3按键控制多位数码管，四位数码管上显示数字由大到小，按键控制移位-3* 3 keys to control a number of digital control, four digital tube display digital descending, key control shift
zuojiayoujian
- 四位数码管左边两位自动增加，右边两位自动减少-Four digital tube left two increases, the right two automatically reduces
xapp199
- writing efficient testbenches
A-4-bit-variable-modulus-counter
- 用Verilog HDL设计一个4bit变模计数器和一个5bit二进制加法器。在4bit输入cipher的控制下，实现同步模5、模8、模10、模12及用任务调用语句实现的5bit二进制加法器，计数器具有同步清零和暂停计数的功能。主频为50MHz，要求显示频率为1Hz。-A 4-bit variable modulus counter and a 5bit of binary adder using Verilog HDL design. 4bit input under the control
VHDL-to-design-detector
- 用VHDL语言设计一个序列“111010”的检测器和该序列的发生器-VHDL language " 111010" to design a sequence detector and the sequence generator
adsawfd
- 用Verilog HDL设计3线-8线译码器，ena是译码器的使能控制端，当ena=1时译码器工作，ena=0时译码器被禁止，8个输出均为高电平 用Verilog HDL设计具有三态输出的8D锁存器。-3-to-8 line decoder, ENA is designed using Verilog HDL the decoder enable control terminal, when ena = 1 time decoder, ENA = 0 time decoder is disa
ewgweg
- 5959计时器及用数码管显示出来其中包括顶层程序和子程序-5959 timer and digital display including the top-level routines and subroutines
Digit_sys_proj-tbird
- T-bird LED by modelsim 6.5e
UDP
- 这是用Verilog HDL编写的程序 利用UDP方法实现四位加法器-This is written in Verilog HDL programs Use UDP method four adder
fir
- 利用VHDL和Verilog HDL语言实现FIR滤波器-Using VHDL and Verilog HDL language to realize FIR filter
addr_rtl
- 利用Verilog HDL编写程序 利用assign语句实现加法器-Use Verilog HDL to write programs Using the assign statement adder