资源列表
8051_PLJ
- 本设计基于8051IP Core和FPGA技术结合提出一种等精度频率测量方案，解决了传统测频方法测频精度随频率的下降而下降的问题。-The design is based 8051IP Core and FPGA technology combined proposes a precision frequency measurement solutions solve the traditional frequency measurement frequency measurement accu
my_uart
- 本程序采用Verilog HDL程序编写的串口程序。-The program uses the Verilog HDL programming serial procedures.
IEEE-Std-1364.1-2002-Verilog-RTL-Synthesys
- IEEE Std 1364.1-2002 Verilog RTL Synthesys
IEEE-Std-1364-2001-Verilog-LRM
- IEEE Std 1364-2001 Verilog LRM
IEEE-Std-1800-2012-SystemVerilog
- IEEE Std 1800-2012 SystemVerilog - Unified Hardware Design, Specification, and Verification Language
IEEE-Std-1076.6-1999-VHDL-RTL-Synthesis
- IEEE Std 1076.6-1999 VHDL RTL Synthesis
Xcell-Journal-issue-82
- Xcell Journal issue 82 released by Xilinx.
dianti
- 基于FPGA的六层电梯控制模型 内含波形仿真图形-FPGA-based six-story elevator control model includes a waveform simulation graphics
SSDT
- 同步串行数据发送电路，并行数据输入，串行数据输出。-Synchronous serial data transmission circuit, parallel data input, serial data output.
lab1
- 一个21位先行进位加法器的代码 交作业和毕设必备，自己写的，不完全地方请指出 -A 21-bit carry-lookahead adder code homework and must complete set up, wrote it myself, not exactly place please indicate
motor
- 课程设计 直流电机 pwm verilog -Curriculum design DC motor pwm verilog
cpu
- 简易cpu 课程设计 vhdl modelsim-Easy cpu curriculum design vhdl modelsim