资源列表
vgachar
- 在FPGA内部产生一个有字符的视频，并通过VGA显示到显示屏。-Within the FPGA to generate a character video and VGA display to display.
clock_seg
- 用FPGA分频，做一个有时分秒的时钟，并用数码管显示-FPGA divide a sometimes every minute clock, and digital display
rx_tx
- 上位机与FPGA进行RS232通信，FPGA可以发送与接收。-Host computer and the FPGA RS232 communication, the FPGA can send and receive.
lcd
- FPGA对液晶屏写控制字，并在液晶屏上显示一个字符串This is a test -FPGA control word written on the LCD screen, and displayed on the LCD screen a string This is a test
seven_color
- FPGA产生7条竖色条，分别是7个基本色。并显示到VGA接口的显示器-FPGA generate seven vertical color bar are seven basic colors. And display monitor to the VGA port
div_clk
- 一个20M转16M的时钟分频设计的小程序。有一定的漏洞请大家自行修正-A 20M to 16M clock frequency applet. There are some loopholes Please correct itself
pri_encoder_using_if
- encoder using if - verilog
decoder_using_with
- decoder_using_with verilog code
EDA
- 4位十进制计数器+7段数码管显示,有需要的同学可以参考一下！-4 decimal counter+7 of segment LED display
product-Altera
- ALTERA 产品列表，内有详细参数，用于设计时参考选型-altera products for selecting
Digital_Clock
- FPGA数字时钟完美通过测试。目标板是ZRTECH的EP2C5T144C8 CORE2-5U核心板及PERI1-8KD配套子卡。-The FPGA digital clock perfect pass the test. The target board is ZRTECH EP2C5T144C8 CORE2-5U core board and PERI1-8KD supporting daughter card.
sdram
- SDRAM控制程序！verilog语言，已调通！-The SDRAM control procedures! Verilog language, has been transferred through!