资源列表
cpld-usb
- usb-fpga通讯，从cpld到usb协议芯片slave fifo的通讯过程指导。-The usb-FPGA communication from the CPLD to usb protocol chip slave FIFO communication process guidance.
vhdl-code-for-FFT-32-point
- vhdl code for FFT 32 point
prj_5
- FIFO Using MyFIFO_Block_Memory_v7_1 with verilog code
prj_2
- a practical project using blk_mem_gen_v7_1_Veriloge
randomizervhdl
- Randomizer Vhdl he RTL now is working correctly, and the TB also is working but there is a problem in the sequence of the reset and and the load
lab1
- 电子琴，自动播放，手动播放，录音功能-Keyboard, autoplay, manual playback, recording function, etc.
qdq
- 设计一个可容纳6组(或4组)参赛的数字式抢答器，每组设一个按钮，供抢答使用。 抢答器具有第一信号鉴别和锁存功能，使除第一抢答者外的按钮不起作用。 设置一个主持人“复位”按钮。 主持人复位后，开始抢答，第一信号鉴别锁存电路得到信号后，有指示灯显示抢答组别，扬声器发出2~3秒的音响。 设置一个计分电路，每组开始预置100分，由主持人记分，答对一次加10分，答错一次减10分 -The design can accommodate a group (or groups) participating
Five
- 用Verilog语言写程序，实现对初始时钟的五分频-Verilog language used to write programs, one-fifth of the clock frequency
MATHM60
- 用Verilog语言写程序，实现对初始计数器60进一-Verilog language used to write programs to achieve the initial counter 60 a
Twofenpin
- 用Verilog语言写程序，实现对初始时钟的两分频-Verilog language used to write programs, two points of the initial clock frequency
signal-generator
- Design of DDS signal generator based on VHDL+FPGA, has been through the adjustable, can be directly used, simulation -DDS signal generator circuit design, Verilog source code, can be directly used, simulation
cpu
- 用VHDL写的一个cpu程序，可以在实验台上运行运行，包括各种基本的寻址方式，里面还含有每个模块的波形-Use VHDL to write a cpu program that can run on the bench run, including a variety of basic addressing modes, which also contains the waveform of each module