资源列表
eda
- cpld开发板电路图，刚下载的，还不错，给大家看看。-the map of cpld developed board。
AdControl
- AD7470_7472 采样的verilog 代码，通过硬件调试直接可用的，程序里 定义了100个8位存储器，用于接收采样的数据，当100个数据接收完毕时不在接收 ，并一直开始循环输出 所采数据。用时 修改下就行-FPGA code for analogue and digital conversion,which has been tested with hardware.
EDAFIR
- 采用vhdl代码编写的滤波器仿真，对初学者有一定的帮助。-Vhdl coding using filter simulation, there is some help for beginners.
8051core-Verilog
- 利用VerilogHDL语言，编程实现8051单片机的功能，在FPGA的工程中有广泛的应用-Use VerilogHDL language programming 8051 microcontroller functions in FPGA projects in a wide range of applications
data_transmission
- 并行数据流转换为一种特殊的串行数据流 重点在通信协议的实现上 注意同一时钟驱动几个信号时，若信号需要分别使用跳变沿或电平有效，那么分别用时钟的不同沿进行驱动-Parallel data streams into a special kind of serial communication protocol data stream focuses on the realization of the same clock-driven attention to a few signals,
detect_signal
- 此程序完成一个序列检测的功能，检测10010序列，适当改进，可以用于FPGA中信号检测-This process is complete a sequence of test functions, test 10010 sequence, appropriate improvements can be used for FPGA in the signal detection
FIR_lowpass
- 在FPGA上实现一个FIR滤波器，适当修改滤波器参数，就可以运用于自己的工程中-In the FPGA to achieve a FIR filter, appropriate changes to filter parameters, you can apply your own project
FIFO
- 设计了一个具有双时钟信号，双复位信号的FIFO，用于FPGA中的数据缓冲，RAM的定义是参数型，可以根据自己的需求，修改此参数，完成RAM的容量扩展。程序中有详细的说明-Designed a dual-clock signal, double reset signal FIFO, for the FPGA in the data buffer, RAM is defined as parameter type, according to their needs, and modify this
8BITCONDITIONALSUMADDER
- it is verilog code for 8 bit conditional sum adder using veriwe-it is verilog code for 8 bit conditional sum adder using veriwell
encoder_binary
- 一个简单的FPGA实现的编码器，但程序中有详细的说明，并附有测试凳，可以以此为基础设计更复杂的编码器-FPGA realization of a simple encoder, but the procedure described in detail, together with a test bench, you can as a basis for designing more complex encoder
FINALAB
- it is veri log code for ALU comparator and shift register using veriwe-it is veri log code for ALU comparator and shift register using veriwell
finallab
- introduction to veri well and behaviural modeling code for 4 to 1 mux