资源列表
XilinxSpartan3DevelopmentKit-UsersGuide
- sparatn 3 development board user guide and vhdl language reference guide
chuzuchejijiaqi
- 基于FPGA的出租车计价器设计，有显示路程，费用，等待时间，语音提示等功能。-FPGA-based design of the taxi meter, showing the distance, cost, waiting time, voice prompts and other functions.
vhdl-JPEG-enc
- JPEG Encoder,Here is a quite detailed low level design document for the Core: Low Level Design Document
55593412100vhd
- vhdl编程实例，一共有95个实例。 1_adder 2_adder 3_mul 4_comp 5_mux2 6_reg 7_shiftreg；
CORDIC算法分析
- 基于FPGA的高精度相位差测量算法实现 - (Implementation of high precision phase difference measurement algorithm based on FPGA)
music
- 乐曲播放程序，便于初学者掌握verilog HDL语言的进行数控分频器的设计和使用(The music player program is easy for beginners to master the design and use of Verilog HDL language.)
UART
- 用VHDL实现与电脑串口进行通信。已通过开发板验证正确。开发板时钟50M，波特率19200.-VHDL implementation using serial communication with the computer. Has been verified through the development board are correct.
optsim
- hi it is program for 3X3 multiplication
gray2binary1
- grey to binary in vhdl
Digital-Clock
- 该文档完成了数显电子钟系统设计。能够对S（秒）、MIN（分）、Hr（小时）进行计时，按24小时计时制。采用Top_Down的设计方法。 -The document Digital electronic clock to complete the system design. Able to S (s), MIN (minutes), Hr (hour) time, according to the 24-hour clock system. Using Top_Down design met
VHDL--PCF8563T
- I2C实践，-PCF8563T实时时钟vhdl语言-I2C practice,-PCF8563T real-time clock vhdl language
14-adc
- fpga verilong adc转换程序，带数码管显示 很好学-fpga verilong