资源列表
Xilinx_XUP_V2P
- Please read your package and describe it at least 40 bytes in English.
conv-std-logic
- This the code for convert binary number to integer number using std logic vector function. -This is the code for convert binary number to integer number using std logic vector function.
DC-Adder_Array
- 要求采用快速进位链（Look Ahead）设计一个21位加法器； 2) 采用结构化的设计方法，所有加法器均采用步骤1）的21位加法器； 3) 在加法器阵列中加入流水线结构（Pipelinc），输入连续送数，输出连续出结果，流水线填满后每拍输出一个结果； -1) requires the use of fast carry chain (Look Ahead) design a 21-bit adder 2) the use of structured design metho
verilog-SPI-Controler
- 使用Verilog语言实现的SPI控制器，包括SPI主机和从机代码。-Using the Verilog language implementation of SPI controllers, including SPI master and slave codes.
be59e2f1-3eb0-45bc-ac60-dcd988cd2604
- 很有用的fpga学习资料，初学者必备。可以从代码看起，对学习uart协议也很有帮助。-Fpga learning useful information, essential for beginners. Looks from the code, uart protocol is also helpful for learning.
Convolutionalencoder
- 应用VHDL语言实现的卷积编码器的应用程序-Application of VHDL language implementation of the convolutional encoder applications
count
- 实现各种计数器的vhdl的实现方法,经过验证-many count
UART
- 实现异步串口,异步串口的收发.已经通过验证.-UART
Q
- 制作一个锁存器,常用于地址的所存,上升沿触发-DtoQ
8b10b
- 8b10b编解码，用于光通信和千兆以太网，verilog编写，已验证-8b10b codec for optical communications and Gigabit Ethernet, verilog prepared Verified
vhdl_miaobiao
- 基于FPGA，VHDL实现秒表功能，利用了分频和计数-FPGA, VHDL-based stopwatch function, the use of divide and count
vuhftranciever
- implementation of MMI and intermodule communication in vhf or uhf tranciever