资源列表
ADC_INTERFACE
- it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit. -it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix i
fixed_point_arithmetic
- 该项目启动以便在verilog中创建定点（Q格式）算术模块-This project was started in order to create fixed point (Q format) arithmetic modules in verilog.
BCH_EncDec_Matlab
- bch编解码的完整版，本人已经做过fpga实现，就是按照该程序为原型，绝对可运行-bch decoding the full version, I have done fpga implementation is in accordance with the procedure for the prototype, can certainly run
Desktop
- code for edge detection
FINALAB
- it is veri log code for ALU comparator and shift register using veriwe-it is veri log code for ALU comparator and shift register using veriwell
DMADMA_fanli
- 详细介绍nios DMA范例,很有帮助的.
uart_testbench
- opcore.org "uart16550" 项目的testbench-test bench of "uart16550" project
15-vlsi
- Asynchronous fine grain power gated logic paper get code and logic static used
modelsim
- 一款用于扩频通信发射系统的CPLD程序，基本的QPSK调制-A used in spread spectrum communication system of CPLD program, basic QPSK modulation
rsa.tar
- good working RSA code with testbench
xcv
- verilog编写的状态机检测00100序列. 实现 input:...011000010010000... output:...000000000100100... 并且 用测试模块来验证状态是否正确工作-verilog prepared by the state machine detected 00,100 sequences. Achieve input : ... ... 011000010010000 output : 000000000100100 ... ... a
fir
- this is an vhdl code for fir filter-this is an vhdl code for fir filter....