资源列表
ddc
- 数字下变频，vhdl代码，包含CIC和HF滤波-vhdl
FP_GA
- THis documnt gives the brief details about the fpga technology
m68_k
- motorola m68k VHDL描述-motorola VHDL descr iption m68k
sdram_ctl
- srram cntrol program
scaler
- 针对视频数据的ZOOM IN/OUT模块， 插值算法为双线性或最邻近可选。-For video data ZOOM IN/OUT module, Interpolation algorithm for bilinear or nearest neighbor optional.
bitadder
- verilog code for 4 bit adder
D_Flip
- D触发器建立时间和保持时间检查，D触发器建立时间和保持时间检查-D flip-flop setup time and hold time checks, D flip-flop setup time and hold time checks
PULSE
- 这是一个将6组并行数据串行输出的VHDL源码，配合外部电路可以输出正负脉冲，还附有逻辑图哦。-This is a group of parallel data to serial output 6 of the VHDL source code, with the external circuit can output positive and negative pulses, also with a logic diagram oh.
mulit_18b20
- 温度测量，可以测量20处以上的温度！传回传感器-Temperature measurement, can measure the temperature of 20 or more! Return sensor
NIOS_I2C_SD2405
- 基于NIOS的I2C总线，SD2405实时时钟芯片读写代码。-I2C-bus based NIOS, SD2405 real-time clock chip to read and write code.
Async-FIFO-VHDL
- 异步FIFO VHDL代码实现，包括：async_fifo_show_ahead.vhd， async_fifo_show_ahead_rd_task_logic.vhd，async_fifo_show_ahead_wr_task_logic.vhd， sync_r2w.vhd，sync_ram_std_dc.vhd，sync_w2r.vhd-The asynchronous FIFO VHDL code implementation, including: async_fi
band-filter
- 使用Electronics Workbench 5.0电子仿真软件(EWB)设计的带通滤波器。-Using electronic simulation software Electronics Workbench 5.0 (EWB) design a bandpass filter.