资源列表
delay
- 一个可以把信号拉长任意个CLk的VHDL源码例子。详见说明文档-A signal can be stretched any one CLk the VHDL source code examples. See documentation
multiplier
- verilog program for 8-bit multiplier
clock
- verilog program for real time clock.. select the .v file to view the code.
44keyboard
- 刚写的一个44键盘程序，调了好多天才调出来，给大家提供参考。-Just write a 44 keyboard program, tune out of tune a lot of talent to give you a reference.
LCD
- 用VHDL写的一个显示程序，希望能帮上大家的忙，嘿嘿。-Written in VHDL, a display procedure, hoping that would help everyone a favor on the Hei hei.
FPGApinlvji
- 当年本科时的毕业设计，信号发生器和频率计-The time of the year undergraduate graduate design, signal generator and frequency counter
vhdlclock
- making a simple clock using altera vhdl
fir_9222_sopc
- 基于sopc技术的数字均衡器带通滤波器及12864液晶显示-Sopc technology-based digital equalizer band-pass filter and liquid crystal display 12864
wallace
- it is a multiplier used in RIsc architecture based processor.......
Digital6Counter
- 多功能数字时钟 功能齐全 vhdl fp-Multi-functional digital clock vhdl fpaa
UART-CPLD
- 使用VHDL在CPLD上设计UART的一个项目-VHDL design UART
qiangdaqi
- 四人抢答器，已通过编译，仿真，包括抢答识别、计分、计时、数字显示等功能。-Four Responder, has passed the compilation, simulation, including the answer in his identification, scoring, timing and digital display.