资源列表
ref-ddr-sdram-vhdl
- 用VHDL编写DDR SDRAM Controller的源代码- Compiles DDR SDRAM Controller with VHDL the source code
16位乘法器
- 自已写的一个16X16的乘法器，速度比较慢。初学者练习练习！-own writing an audio Multiplier, speed is relatively slow. Beginners practice practice!
能综合的YCrCb2RGB模块（verilog)_采用3级流水线
- 能综合的YCrCb2RGB模块（verilog)_采用3级流水线,用fpga做小数运算，还有就是流水线技术 -can YCrCb2RGB integrated module (Verilog) _ used three lines, they simply do with fractional arithmetic, there is pipelining technology
SSP_PL022-REL1V0
- SSP_PL022-REL1V0.zip
scrambler
- 通讯领域很多对原始数据进行加饶，加饶的多项式可以有很多种。上面是一种实现，可以参考实现其它加饶的多项式， 同理如果实现解扰可以反过来
FPGA designer
- 一个LED闪烁程序，使用计数器方式呈现，以第25位作为标志位，控制LED闪烁
Car Parking Module FPGA Zedboard
- This project is based on the car parking module it is working condition
VIRTUAL INPUT OUTPUT VERILOG CODE
- THE IS CODE THAT USED THE VERILOG WHERE VIO FUNCTION USED
Designing CLock
- Clock designing for the Verilog Zedboard
PWM Motor feedback
- Verilog code for learning for purpose