资源列表
risc8_tar
- 用Verilog HDL完整的写出了cpu -Using Verilog HDL to write a complete cpu
dds_test
- 使用图形编辑法（block模式）编写的全套DDS部分，应用于FPGA，开发环境为QuartusII。形象直观，用户可以直接生成代码另行应用-The use of graphic editing method (block mode) part of the preparation of the full range of DDS used in FPGA, the development environment QuartusII. Visual image, the user can be d
VGA123342
- 该段代码非常详细的描述了VGA显示器怎样用VHDL来描述。-The above code is very detailed descr iption of the VGA display to describe how to use VHDL.
count64
- 将5MHz时钟信号分频后得到1.6/3.2秒可选的同步信号，还可接外接同步信号对其进行强制同步-To 5MHz frequency clock signal 1.6/3.2 seconds after the optional sync signal, external sync signal can then be forced synchronization
modifiedBoothMultiplier
- verilog code for modified booth multiplication using maxplus2
shiyan3
- 为c++类模块的调用，必须在c++环境中使用-For c++ class module of the call, must be c++ environment
Ram_interface
- VHDL Ram interface which devaloped for 256K ram -VHDL Ram interface which devaloped for 256K ram
CRC
- 关于通信系统中循环差错检测的vhdl仿真程序，内容十分完整-Communication systems on the circle of error detection of vhdl simulation program, very complete
elevator
- 这是一个小课程设计，关于电梯控制的vhdl仿真程序，内容十分完整-This is a small curriculum design, on the elevator control of vhdl simulation program, very complete
wave_generator
- 这是一个关于信号发生器的vhdl仿真程序，内容十分完整-This is a signal generator on the vhdl simulation program, very complete
suanfa
- 算法硬件实现，学习的好资料，来自北航夏宇闻老师，VERILOG。-Algorithm for hardware implementation, learning good information, hear from teachers BUAA Xia, VERILOG.
THS1206
- FPGA来实现数据采集，AD采用TI公司的THS1206，高速并行AD，内含16字FIFO，降低硬件复杂度。-FPGA to realize data acquisition, AD using TI company s THS1206, high-speed parallel AD, containing the 16-character FIFO, to reduce hardware complexity.