资源列表
dac
- 0～5伏可调数字电压源，以5伏为基准电压，数码管显示当前电压值，使用VHDL语言实现，程序都加了注释，方便阅读。 -0 ~ 5 V digital voltage source adjustable to 5 V for the voltage reference, digital tube displays the current voltage value, the use of VHDL language, the program notes are added to facilita
eff1
- 利用Verilog实现的跑马灯，从护栏管的一端循环到另一端。其他类似此类的循环语句基本一样。-Marquee achieved using Verilog, from one end of tube to the other end of the cycle. Other similar expressions of such basic, like the cycle.
FPQ
- 基于FPGA的数控分频器，可以吧一个时钟信号分成不同频率的时钟信号。-FPGA-based digital frequency divider, a clock signal can now be divided into different frequency clock signals.
sin
- 基于FPGA的正弦波发生器，可以产生不同频率的正弦波。-FPGA-based sine wave generator, can produce different frequency sine wave.
Shuma
- 完整的电子钟程序，包含报时、定时、闹表的功能，其中包含了二十四进制，60进制计数器的设计，和顶层文件-Complete procedures for the electronic bell, including the time, from time to time, to make the function table, which contains 24 hexadecimal, 60 hexadecimal counter design, and top-level document
Adder_Verilog
- 对于Verilog初学者非常实用的代码，帮助了解许多常用的加法器-Very useful for beginners Verilog code to help understand the many commonly used adder
RS204_188
- 可以省去开发者编写译码器的时间，高效的译码器给开发者带来便利-Save developers time to prepare decoder, efficient decoder to facilitate developer
Multiple
- 高效的乘法器设计，既节约面积，又提高性能，同时减少开发周期-Efficient multiplier design, both to save space and improve performance while reducing the development cycle
GF_Multipe
- 加德罗域乘法器提供了一种新型的乘法器设计模式-Multiplier加德罗domain to provide a new design of the multiplier model
music
- 通过一个晶振信号的输入，经过分频和音高的编程，实现输出音乐。用外置的蜂鸣器经行发音。-Through a crystal input signal, the frequency and pitch programming to achieve the output of music. After the buzzer with external line pronunciation.
PROJ
- 1、本实验模拟正弦函数发生器 2、使用逻辑分析仪查看波形 3、/proj/simulation目录中可以在modelsim中仿真-1, this experiment simulated sine function generator 2, using the logic analyzer to view waveform 3,/proj/simulation directory of simulation in modelsim
led_key
- quartus下的按键控制led的工程文件-quartus button under the control of engineering documents led