资源列表
FPGA_SOPC_starter
- 很详细的入门文章 对于初学者是不错的参考 也可以下载altera handbook 同样有更经典的案例FPGA_SOPC_starter-FPGA_SOPC_starter
nios2_hardware_tutorial
- NiosII硬件开发指南，同样可以到Altera官方网站下载最新版的turorial nios2_hardware_tutorial-nios2_hardware_tutorial
embedded_design_handbook
- embedded_design_handbook Altera NiosII嵌入式系统SOPC开发handbook-embedded_design_handbook
FPGA27examples
- FPGA很有用的27个实例，对于新手或者迷茫的人应该有点用处-FPGA is used for 27 examples of confusion for the novice or the person should be a bit useless
vhdl
- Very high speed integrated Hardware Descr iption Language (VHDL) -是IEEE,工业标准硬件描述语言 -用语言的方式而非图形等方式描述硬件电路 容易修改 容易保存 -特别适合于设计的电路有: 复杂组合逻辑电路,如: -译码器,编码器,加减法器,多路选择器,地址译码 -Very high speed integrated Hardware Descr iption Language (VHDL)-
chuzhuche2
- VHDL语言设计的出租车计费器，能模拟汽车启动、停止、暂停、车速等状态，能预置起步费、每公里收费、车行加费里程，能实现计费功能。功能强大，初学者适合看一看。-VHDL language design taxi billing, and can simulate the vehicle to start, stop, pause, speed, etc., and to preset the initial charges, fees and charges per kilometer, plus
fifomodule
- 定义了一个FIFO和相关的读写功能,比较实用,可直接作为模块使用-define a FIFO that contains the relative read and write functions, and it can be used as module directly in ISE.
ptos
- 要求：并行输入1 byte，串行输出，无数据时输出高电平，输出格式1100+8bit+奇偶校验+0011（停止位）串行输入，并行输出，检测是否奇偶校验错误，是否有帧传输错误传输每bit数据占16个clock周期 -Requirements: parallel importation of 1 byte, serial output, no data output high, output format 1100+8 bit+ parity+0011 (stop bit) serial inp
pciug159
- XILINX ISE生成PCI-CORE时产生的用户文档,帮助编写PCI通信用户逻辑,非常有用-XILINX ISE generation PCI-CORE generated user documentation to help users prepare PCI communication logic, a very useful
QAM
- VHDL-AMS Behavioral Modeling and Simulation of M-QAM transceiver system
VHDL_examples
- contain simple examples in VHDL languge
FFs
- A verilog example code of a shifter register using 3 FFs. Commented-A verilog example code of a shifter register using 3 FFs. Commented!!