资源列表
pipelined_fft_64_latest.tar
- pipelined fft 64 latest OK
PRF_CTL
- 产生时序脉冲组，设计人员可以根据自己的需要，改变相应的数值，可以得到自己想要的脉冲组-Generates timing pulses, designers can according to their needs, change the appropriate values, you can get what you want in the pulse group
ds18b20Plcd
- 温度控制系统.运用ds18b20温度传感器将实时温度送入FPGA中，再将温度显示出来-Temperature control systems. Use ds18b20 temperature sensor into the FPGA in real-time temperature, then the temperature is displayed
AD9858_point
- DDS采用AD9858元器件，使用VHDL编写两点切换点频程序。-AD9858 DDS using components, the use of VHDL frequency switching point two procedures.
YSW
- 基于FPGA的使用VERILOG语言编写的四联十进制加法的程序-Decimal addition quadruple
add16
- 基于FPGA的VERILOG语言的四联十六进制的加法程序-Based on quadruple hexadecimal addition program the FPGA VERILOG language
SegLed
- 数码管的动态显示Ip，你可以例化到设计中需要的工程里-Dynamic digital display Ip, you can instantiate the need to design projects in
subtraction
- 基于FPGA的VERILOG语言的四联十六进制的减法程序-Based on quadruple hexadecimal subtraction process of FPGA VERILOG language
button33
- 基于FPGA的VERILOG语言的3*3按键程序-3* 3 keys based on FPGA VERILOG language program
SECOND
- 基于FPGA的VERILOG的一秒亮一个LED的程序-FPGA-based VERILOG one second light an LED program
VGA
- 本科毕业设计，简易逻辑分析仪，重点在于用CPLD搭建显卡，输出VGA信号驱动显示器显示逻辑波形-A design for LA,use cpld to generate VGA signals.
or_g
- it contains or gate, multiple input output, counter 4-bit 8 bit, parallel adder 4 -bit, 8 bit