资源列表
Half_Frequence
- 本程序基于VHDL语言，设计分频器，其中包含半整数分频占空比不为50 奇数分频占空比为50 任意小数分频 -The program is based on VHDL language design divider, which includes half-integer divider 50 duty cycle is not odd frequency 50 duty cycle any fractional
moore
- moore状态机，quartusii上仿真通过-moore state machine
FPGA-multiplexer-bus
- FPGA睿智助学板IV代总线与多路复用器Quartus II工程-Generation IV FPGA wise student boards the bus with the Quartus II project multiplexer
vganew
- vga code for FPGA SPARTAN 3E
AT510-BU-98000-r0p0-00rel0
- CORTEX-M0处理器官方公开的源代码包！采用模糊网表生成，不可读但可综合可仿真可流片，还有testbench示例，很宝贵的资料！-CORTEX-M0 processor officially open source code package! Netlist generated by fuzzy, unreadable but comprehensive simulation can be taped, as well as testbench example, very valuable
PS2mouse
- 应用FPGA开发版的PS2鼠标处理模块，主要讲输入的鼠标ps2_clk ps2_data信号转换为x y方向上的相对位移量-Application development version of PS2 mouse FPGA processing module, the main speaker mouse ps2_clk ps2_data input signal is converted to a relative displacement of the x y direction
musicplayer
- 利用FPGA开发板做的音乐播放器，可以播放四首简单的歌曲，通过外接耳机即可收听-Using FPGA development board to do a music player that can play four simple song, you can listen through external headphones
transaction class.sv
- transaction class for APB
4 bit arbitar
- arbitar for code master block
sv code for ic
- System verilog code for generator class
final
- 实现16阶的fir滤波器，分模块例化并且最终以原理图的形式实现并仿真-Fir filter stage 16, sub-module instantiation and eventually realized in the form of schematics and simulation
crc-16b-parallel
- CRC generator in verilog hdl