资源列表
uart_tx
- uart transmitter module in verilog hdl
uart_rx
- receiver module of uart protocol in verilog hdl
movingobj
- moving object tracking on fpga
Digital-competition-responder
- 数字式竞赛抢答器的VHDL程序及实验报告，本抢答器是最多可容纳5位参赛者的数字式抢答器，在QUARTUS II平台中进行了仿真-VHDL procedures and lab reports Digital contest Responder, the Responder is for up to five contestants digital Responder, a simulation platform in QUARTUS II
LCD_clock
- FPGA秒表，LCD1602显示,就是简单的有个暂停键，按一下开始再按一下暂停-FPGA stopwatch, LCD display
shift-register-
- 含同步预置功能的右移移位寄存器设计Verilog设计-Verilog right shift
RS232code
- 串口通信VHDL代码，经过调试运行正常，采用ISE13.4编写-Serial communications VHDL code, after debugging and running properly, using ISE13.4 write
fft-IPcore
- verilog编写，基于ISEfft的ip核研究，数据生成采用matlab，有仿真截图-verilog written, ip nuclear research ISEfft based on data generated using matlab, there are simulation screenshot
key_led
- 基于xilinxFPGA测试通过，按键消抖动，verilog编写，控制流水灯-Based xilinxFPGA test, the key jitter elimination, verilog prepared to control water lights
12_sdram
- 黑金开封版配套程序12，定时器的程序。与大家分享一下-Black Gold Kaifeng version supporting program 12 timer programs. Share with you
15_pwm
- 黑金开发板配套程序15，PWM的使用，与大家分享。-Black gold development board supporting program 15, PWM used to share with you.
phasevocoder
- PHASE VOCODER的FPGA实现-PHASE VOCODER FPGA Implementation