资源列表
frq_cnt
- Frequency Counter in VHDL.
DE2_NET
- document is waveform file testing for any RLE encoder
iic总线源代码
- 此文件是iic总线驱动的源代码文件，iic.c 可以读写控制多个挂在总线上的器件。
Pwmleddim
- This PWM Coltrolled Led Light Processing Alogothim we are sometimes nead a Led bight that is controlled with PWM and I Use this Algoritm to make various Led Light source -This is PWM Coltrolled Led Light Processing Alogothim we are s
counter100
- VHDL语言 FPGA 一百进制计数器 元件例化方法-VHDL, FPGA hundred cases of binary counter element method
DIV16
- DIV在编程中又叫做整除，即只得商的整数。DIV16实现16位的整除，一般用在分频。-DIV in the programming, also known as divisible, that' s only an integer. DIV16 to achieve 16-bit divides, usually used in frequency.
ALU_VERILOG_COCOTB
- ALU written in Verilog HDL and tester written in python using the cocotb library
jianpanjiekoups2
- 【原创】44矩阵键盘接口程序（VHDL）(2009-10-27 201747) 标签：矩阵键盘vhdl杂谈 初级版：支持输入三个十位数字组成的两个操作数加减与或比较运算，零占位不可省。 程序代码：-【Original】 44 matrix keyboard interface program (VHDL) (2009-10-27 201747) Tags: Matrix keyboard vhdl Zatan junior version: support the i
dianzifayinxt
- vhdl设计用的，可以用于课程设计，帮助完成课程。-vhdl design and curriculum design can be used to help the completion of the course.
FPGA_UART
- 用Verilog语言实现的FPGA UART独立收发模块 思路简单，代码简洁。在Lattice LFE3EA VERSA开发板上验证通过,编译器Lattice Diamond. 功能：串口收到数据后立即回传，此后每一秒串口数据+1再发送。-Using Verilog language independent of FPGA UART transceiver idea is simple, concise code. Development board in Lattice LFE3EA
fbo
- nand flash 的擦出，读，写，拷贝等基本操作。-nand flash erase, read, write, copy and other basic operations.
LIBRARY-IEEE
- 底层文件2：h_subber.VHD实现一位半减器 顶层文件：f_subber.VHD实现一位全减器 -The underlying file 2: h_subber.VHD-to achieve a half- Top-level file: f_subber.VHD the realization of a full subtracter