资源列表
test_cnt
- 仅为VHDL语言的测试程序，工初学者使用，比叫简单了。-VHDL language is only testing procedures, the beginners to use than a simple call.
countdown
- Please read your package and describe it at least 40 bytes in English. System will automatically delete the directory of debug and release, so please do not put files on these two directory.
ExampleCode_DDS_AD9954
- 这是一个关于AD9854的测试程序，里面包含了AD9854基本功能的测试-This is a test program on AD9854, AD9854 which contains the basic functions of the test
VHDLFrequencycircuit
- 分频电路的VHDL设计,在你的设计中,如果有用到分频电路的话,他将帮组你了解分频电路
jishu
- 实现自动售货机的计数模块.en为接受信号，当投币开始时投币模块发出信号，计数模块开始工作，当计数到30时向控制模块发出t信号。Clr为控制器发送给计数模块的一个信号，当clr为1时，计数器归零。Clk为分频模块发送的时钟信号-failed to translate
Electronic-clock-simulation
- 1、LCD显示“时钟”样式，时针、分针、秒针显示实时时间； 2、LCD显示“数字钟”样式，动态显示年、月、日、时、分、秒； 3、显示时间可以修改并使“时钟”与“数字钟”保持一致； 4、LCD下方动态显示小组成员姓名、学号等个人信息。 -1, the LCD displays "clock" style, hour, minute, second hand, displays real time LCD display digital clock style, dynamic
LCD_fullscreen
- 这是本人写的可显示128*64LCD全屏汉字的程序,直接下到片子里即可出现象(需自己定制ROM).想显示第二屏的话只需加一个状态即可.-I write this is the display of 128 * Embedded full screen characters procedures, directly to the unit under the blankets will be out phenomenon (it-yourself customized ROM). to the s
URAT
- 串行通信接口UART设计，串行通信接口是指将构成字符的每个二进制数据位，依据一定的顺序传送的通信方法。-UART serial communication interface design, serial communication interface refers to the form of binary data bits per character, based on a certain order to send the communication method.
uart
- verilog hdl 编写的串口接收发送-send rec data with verilog hdl
430FF123
- msp430169实现FFT代码！07全国电子设计大赛程序代码！-msp430169 achieve FFT code! 07 code national electronic design contest!
conversionandtesting-procedures
- 实现32位串行输入，1024位并行输出的VerilogHDL源程序-32-bit serial input, 1024-bit parallel output VerilogHDL source
Pipeline-2.zip
- Pipeline processor verilog components ,Pipeline processor verilog components