资源列表
SRT
- verilog code radix-2 SRT divider input [7:0]Dividend input [3:0]Divisor output [4:0]Quotient output [8:0]Remainder -verilog coderadix-2 SRT dividerinput [7:0] Dividend input [3:0] Divisor output [4:0] Quotient output [8:0] Remainde
icache
- ARM9指令Cache缓存模块的Verilog代码-cache verilog for ARM
消抖通用函数XIAOPRO：
- EDA中很重要的小程序，保证按键可靠性，防止抖动误差信号产生，外部信号输入时必用此消抖函数-EDA very important small procedures to ensure that key reliability and prevent jitter error signal generated, the external input signal must use this function Consumers shiver
Priority-encoder
- 用VHDL语言编程来实现优先编码器的功能。-VHDL language programming to achieve priority encoder function.
characters
- 一个是发送单个字符的，一个是发送任意长度字符串的-One is to send a single character, a string of arbitrary length is sent
DS18B20-VHDL-program
- DS18B20的VHDL程序,很好，简短易懂。-DS18B20 VHDL program, well, brief and easy to understand.
bsm
- it is the verilog code for a Base Selection Module
fpgadrv
- arm平台下对FPGA的linux驱动。fpga实现多内核的仲裁策略-platform for FPGA-arm linux driver. fpga arbitration multi-core strategy
8b10_enc
- 8b1ob编码，广泛用于通信。是现有传输的常用编码方法-8b1ob
PROG
- USED TO CALCULATE DELAY
LCD-1
- PIC控制LCD12864液晶显示器显示-PIC LCD display control LCD12864
viterbi_soft
- 维特比译码器，调用IP核，软判决输入，开发平台Xilinx Spartan-6系列FPGA-viterbi decoder, using IP core resource, soft decision input,develop platform is Xilinx Spartan-6 series FPGA