资源列表
uart
- VHDL编写的异步输入输出接口控制程序 从网易博客上下的-VHDL write asynchronous input and output interfaces control the process from top to bottom Netease blog
wishbone_m4_s8
- wishbone 骨幹部份 RTL 源碼, 以verilog 寫成, 自創. 支源 4 master 及 8 slave-wishbone core, write by verilog, support 4 master and 8 slaver. language: verilog.
And-serial-converter
- 实现1024位并行输入，32位串行输出的verilog HDL程序 并带有其测试程序-Achieve 1024 parallel input, 32-bit serial output verilog HDL program and with the test procedures and serial converter
PWM
- 自己写的一个pwm模块，verilog的，是用于无刷电机控制的。
uart
- 用vhdl实现的串口通信程序,可以综合并下载到FPGA运行.-Achieved using VHDL serial communication procedures, can be synthesized and downloaded to the FPGA to run.
frequency5x2
- frequency5x2实现频率的分频，5*2即实现10分频，主要用于满足有些控制类的频率时钟。-frequency5x2 realize the frequency divider, 5* 2 frequency of achieving 10 points, mainly used to control the class to meet some of the frequency of the clock.
Traffic_Light
- 根据城市的十字路口各部门和在不同时间的交通流量，智能交通灯控制方案，并给出基于VHDL语言，采用层次结构设计的QuartusⅡ模拟思想。-According to the different branches of city’s intersections and the traffic flow at different times, the program of intelligent traffic light controller based on VHDL is given and s
formula
- 3.8 乘法口诀答题器1602LCD显示-3.8 device 1602LCD show answer multiplication formulas
VHDL
- 给芯片指令，通过输入4X4键盘输入不同的值来得到占空比 不同的信号-Instructions to the chip, 4X4 keyboard by entering different values ??to get different signal duty cycle
293
- 使用293作为驱动芯片 驱动步进电机或者直流电机-Use 293 as the stepper motor driver chip drives or DC motors
CLK
- QuartusII平台verilog语言实现的CLK下降沿测试-CLK falling edge QuartusII platform
VGA_7123
- verilog adv7123 VGA 彩条测试程序-the verilog adv7123 VGA color bar test procedures