资源列表
16x4-register-VHDL
- 16x4的寄存器的VHDL硬件描述语言的实现，可以用quaturs实现。-16x4 register based on VHDL
IICVHDL
- IIC，给予VHDL的IIC的实现，很好的资料-NO
AdaptiveLMSequalizer
- 通信中的用的LMS均衡算法VHDL实现，代码不长，很容易看懂-Communication with the LMS equalization algorithm to achieve VHDL code is not long, it is easy to understand
RS232RefComp
- rs232基于vhdl语言的 uart通信模块 -language based on vhdl uart rs232 communication module
sigma-delta-modulator
- 实现SIGMA-DELTA Modulator的veriolog代码-sigma-delta moudulator for RFPLL
LAPS
- 自己实现的一个简单LAPS协议处理器,VHDL语言实现-Their implementation with a simple LAPS protocol handler
8b10b_enc
- vhdl语言编写，8b10b解码器模块设计-vhdl language, 8b10b Decoder Module
ethernet2
- ethernet using vlsi fpga xilinx boards
machine_etat
- 状态机 idle->edge->one -The state machine idle-> edge-> one
verilog_UART
- This Verilog HDL descr iption implements a UART Version 1.1 : Original Creation 2.1 : added comments
Altera_FIFO
- Altera FIFO的多极级联，实现多个FIFO之间的数据传输。-Altera FIFO multi-polar cascading between multiple FIFO data transmission.
76_PID.zip
- VHDL描述的PID算法，这是一种常用的控制算法,VHDL descr iption of the PID algorithm, which is a commonly used control algorithms