资源列表
post_norm_addsub
- 浮点加减运算的后规格化VHDL程序源代码，很不错，希望对大家有用-Floating-point addition and subtraction operations after the standardized VHDL source code, it is good, I hope all of you a useful
fir_csd
- vdhl实现FIR，乘法器采用CSD编码，在资源紧张情况下，可省去很多资源-vdhl achieve FIR, multiplier using CSD coding, in the case of resource constraints, can save a lot of resources
VHDL
- 运用VHDL描述函数发生器的各个波形，可有构成多功能函数发生器。-VHDL descr iption of the use of various function generator waveforms, can constitute a multi-purpose function generator.
dongtaishumaguan
- 用verilog HDL编写的基于fpga的动态数码管显示程序。-Verilog HDL prepared with fpga based digital control of dynamic display program.
sin_gene
- 读取mif方式，产生正弦信号的vhdl程序-Read mif way to generate sine signal vhdl program
ALU
- verilog硬件仿真，实现32-bit RISC微处理器的算数逻辑单仿真元(ALU),实现加减运算、逻辑运算、移位运算。仿真级别为RTL级。-verilog hardware simulation, to achieve 32-bit RISC microprocessor arithmetic logic one simulation element (ALU), to achieve addition and subtraction operations, logic operations
des
- 具有所有的DES等加密解密运算操作实现，加密，解密等运算-verilog DES encrypt
StepperMotorDrive
- VHDL code for sptepper motor
ddr_data
- This VHDL or Verilog source code is intended as a design reference // which illustrates how these types of functions can be implemented. // It is the user s responsibility to verify their design for // consistency and functionality through the
CRC16-0_5_12_16
- 包含16位CRC的并行实现和串行实现，并有测试程序。-Includes 16-bit CRC of the parallel and serial implementation to achieve, and test procedures.
2uart
- 实现数据在两个串口之间的转发功能，很快速，相当于交换机。-Between the two serial data forwarding, very fast, the equivalent switch.
FAS
- Frequency Analysis System verilog code