资源列表
Micro_uart
- Micro-uart source code
PCI-XIEYI
- PCI协议中文版的，还有一个有关PCI的PPT，一起放在文件里，比较好。-PCI agreement of the Chinese edition, and a relevant PCI s PPT, together within the file, better.
traffic_light
- 用Verilog HDL语言写一个交通控制灯的状态机。十字路口，红绿灯，带倒计时功能，也可以自行变换亮灯时间。-Verilog HDL language used to write a traffic control light state machine. Intersections, traffic lights, with the countdown function, you can also change their own light time.
FPGA_Clk
- 基于Cyclone EP1C6240C8 FPGA的时钟产生模块。主要用于为FPGA系统其他模块产生时钟信号。采用verilog编写。 使用计时器的方式产生时钟波形。 提供对于FPGA时钟的偶数分频、奇数分频、始终脉冲宽度等功能。-Based on Cyclone EP1C6240C8 FPGA' s clock generator module. Is mainly used for the FPGA system clock signal generated in other
datread_display
- 基于FPGA系统数字温湿度传感器显示程序-Digital temperature and humidity sensor display FPGA program
FPGA
- FPGA中数字收发机设计，包括了编码解码，调制解调，串口收发-Digital transceiver design
02-NEC_1999_B
- 数字有效值电压表（1999年B题）,本例程的rst(复位)键位于拨码开关的第1位(最右边),高电平有效。-Digital rms voltmeter Problem B (1999), the routine rst (reset) button is located in one of the DIP switch (far right), active high.
vhdlcode
- mutibit flipflop for combining 50ff s in a single clock
an483
- The Altera® Triple Speed Ethernet (TSE) data path reference design provides a sample SOPC Builder system using the Altera TSE MegaCore® function with two serial transceivers. This reference design demonstrates the operation of the Alte
VHDL_2Ddwt_ALL
- 這是一個DWT的Verilog code,它的主要功用是PC與FPGA之間的DWT程序的溝通與傳輸
The-state-machine-sequence-detector
- 状态机实现序列检测器。设计一个一个左移移位寄存器，用硬件设备上的两个拔码开关，预置一个8位二进制数作为待检测码，随着时钟逐步输入序列检测器，8个脉冲后检测器输出结果。-The state machine sequence detector. Design a left shift register, two on the hardware DIP switch and preset an 8-bit binary number as to be detected code, as the clo
FLASH_model
- 模拟flash读写等时序，学习如何操作该芯片，芯片是n25q系列，欢迎大家下载学习