资源列表
8051_test2
- 简单的8051的内核测试，已经验证通过，VLOGER编写-8051 simple test of the core, has been adopted to verify, VLOGER prepared
EDA_VI
- FPGA外围PROTEL电路图 元器件库-FPGA external circuit components library PROTEL
shumaguan.rar
- 用CPLD驱动数码管，实现从0000计到9999，数码管是用动态显示，程序用VERILOG完成的,CPLD drives with digital control, of from 0000 to 9999, digital control is a dynamic display, the program completed with VERILOG
S16_ADC
- 用Verilog HDL语言编写的AD转换器，可以再Xilinx芯片实现，用ISE软件环境下开发-Using Verilog HDL language AD converter, you can then Xilinx chip, with the ISE software development environment
MOTO3--bujin
- 运行于Altera Cyclone FPGA平台,顶层为原理图方式，模块由VHDL编写的步进电机驱动程序。-Running on Altera Cyclone FPGA platform, the top of the schematic way, module consists of VHDL stepper motor driver.
uml-2-pour-les-developpeur
- Ebook, UML 2 pour les developpeurs, bonne lecture
8-way-responder
- 基于FPGA实现8路抢答器功能 使用芯片为EP2C8Q208C8N,实现40秒内8路抢答功能，八路键盘输入，使用Verilog语言编程，本例子有工程文件、仿真、波形，经过测试可以使用。-8 based on FPGA Responder feature uses chips EP2C8Q208C8N, 40 seconds to achieve 8 Responder features eight keyboard input, using Verilog language programm
Horloge_1_A
- Timer vhdl 24hours with alarm_setup CDSE_powaa !
ps_music_ram
- 用ps/2键盘实现电子琴，利用ram可读出预存的曲子，也可以可写如弹凑的曲子-With ps/2 keyboard to achieve organ, using the ram read out the stored song, it can be written as the song playing Minato
lcd12864_hanzi_zifu
- 基于vhdl的12864 字符和汉字显示程序，带字库，亲测可用-Based vhdl 12,864 characters and character display program, with character, pro-test available
codeacq
- 实现扩频通信系统中的码同步。应用vhdl语言，可以运行-Spread spectrum communication system code synchronization. Application vhdl language, you can run
RGB2Y_lattice
- 这是基于lattice fpga数据转换的一个模块，将rgb888转成标准的yuv中的亮度y。整个工程在diamond2.0版本下编译运行。-This is based on a modular lattice fpga data conversion, it will turn into a standard rgb888 yuv luminance y. The whole project is compiled to run under diamond2.0 version.