资源列表
RTL
- 256位有符号整数乘法器，个人学习时编写，接口为IPBUS，用verilog语言编写-256-bit signed integer multiplier, when writing individual learning, the interface IPBUS, with verilog language
shejishengjiangji
- 对电梯的基本功能进行了实现，并把电梯的一些特殊功能进行了改进，这是本人的毕业设计程序。-The basic functions of the elevator to achieve, and to lift some of the special features have been improved, this is my graduation project process.
7seg-and-display
- key matrix with lcd using PIC microcontroller
ballgame
- 用VHDL语言编写的弹球游戏，控制挡板接住在屏幕上反弹的小球。 显示输出为标准VGA信号，可直接连接VGA显示器。 可用QuartusII软件下载到FPGA中进行实现。
VHDLSourceCodeForADConverterdac8840
- 一个数模转换器的vhdl源码 一个数模转换器的vhdl源码
8b10_enc
- This program is used to do encoding according to 8B/10B protocol. The program has been written in VHDL
divded-VHDL
- 一个简单的ＶＨＤＬ分频模块，可以嵌套自己的子程序实现任意分频-a simple VHDL-frequency module, which can be nested subroutine achieve their arbitrary frequency -
dianzishezhong
- 电子时钟 EDA 基本要求： 24小时计数显示； 具有校时功能（时，分） 附加要求 1、秒表功能（复位，计时
fenpin
- 此程序是用硬件描述语言VHDL编写的分频程序，实现了不同的频率输入。-This procedure is the preparation of hardware descr iption language VHDL sub-frequency procedures, to achieve a different frequency input.
1
- 通过ADC0809的通道0采集电位器的值，并将其处理后通过DAC0832输出，该输出直接连接到ADC0809的通道1，并将IN0和IN1采集到的数据分别在LED和CRT上显示。-Channel 0 capture by ADC0809 potentiometer value and processed through the DAC0832 output, the output directly connected to the ADC0809' s Channel 1, and IN1
7-segment-display-0-to-9
- 7段数码管显示0到9的数字，已经通过测试，可以实现仿真-7-segment display 0 to 9, have been tested, simulation can be achieved
spi_slave
- spi(serial peripheral interface) slave unit with Verilog-HDL