资源列表
a
- booth multiplier vhdl code
b
- vhdl code of multiplier
uart_nbit
- 用verilog语言写的串口通信程序,包括收发两个模块,可用于FPGA的通信中,可通过程序设置收发的位数,有很好的扩展性.-Verilog language used to write serial communication program, including the sending and receiving two modules can be used for FPGA communications, you can send and receive through the progr
scan
- 分时总线切换电路。将3个四位二进制数据分时送到七段显示译码器电路和芯片外部的译码驱动电路，-Sharing the bus switching circuit
camera-code-fpga
- 一个简单的摄像机代码，通过fpga控制，通过vga显示到显示屏上-A simple camera code, through fpga control, displayed on the screen via vga
UART
- General purpose UART written in Verilog Libero core generator.-General purpose UART written in Verilog Libero core generator.
chuzuche
- 出租车计费器的源代码，实现测速计价，时间的显示，显示的切换等功能-The source code of the taxi meter, tachometer pricing, time display, the switch functions
roms
- 一个简单的ram的VHDL描述，希望对大家有点帮助-A simple ram s VHDL descr iption, I hope all of you a little help
uart_txd_rxd.zip
- 将接收到的并行数据转换成串行数据来传输。消息帧从一个低位起始位开始，后面是5~8个数据位，一个可用的奇偶位和一个或几个高位停止位。接收器发现开始位时它就知道数据准备发送,Converting the received parallel data into serial data to transmit. The message frame from a low start bit is followed by 5 to 8 data bits, parity bit, and one of th
Four-adder-and-four--counter
- 4位全加器和计数器的verilog的例程，还有四位全加器的仿真程序。-Four QuanJia device and counter verilog of the routines, and four QuanJia device simulation program.
liushuixian_mul
- 流水线乘法器的VHDL实现，希望对你会有用！-Pipelined multiplier in VHDL implementation, you will want to use!
2mxulie
- 基于CPLD的数字通信系统 2m序列 用VHDL产生 2m序列信号-CPLD-based digital communications systems using VHDL generate 2m sequence signal sequence 2m