资源列表
music
- 基于FPGA的乐曲发生器设计，以 EDA 技术为核心的能在可编程 ASIC 上进行系统芯片集成的新设计方法-FPGA-based music generator designed to EDA technology as the core of the ASIC can be carried out in a programmable system-on-chip integration of the new design method
VHDL06
- 16×4bit的FIFO设计代码，学习代码，请在下载24小时后删除。-16 × 4bit the FIFO design code, learning the code, please delete after 24 hours to download.
vending_machine
- 自动售货机模型，可以设置商品价钱及数量。0.5元及1元投币。可以返回最多1.5元。-Vending machine model, can set the price and quantity of goods. 0.5 yuan and 1 yuan coin. Can return a maximum of 1.5 per head.
minimigJ_source_04_08_2008
- Verilog, c and asm source codes of the Minimig system, a fpga implementation of the Amiga computer. Version minimig-j used on the Minimig fpga board.
packer
- verilog data packer verilog data packer-verilog data packer verilog data packer verilog data packer
fpga64_027
- VHDL source codes of the FPGA64, a fpga implementation of the C64 computer. Version for the c-one fpga board.
T65_v302
- VHDL source codes of a 65xx compatible cpu core. Version 302.
SubDDS
- generate the sine wave using DSP Builder
genode-fx-2009-03
- Genode FX is a composition of hardware and software components that enable the creation of fully fledged graphical user interfaces as system-on-chip solutions using commodity FPGAs.
FPGA_DDR_SDRAMverilog
- 基于Xilinx FPGA的DDRSDRAM的Verilog控制代码，使用的FPGA为Virtex-4，实现对DDRSDRAM的简单控制（对一系列地址的写入和读取）。-Xilinx FPGA-based DDRSDRAM the control of the Verilog code, the use of the FPGA for the Virtex-4, to achieve a simple DDRSDRAM control (on a series of addresses to wr
addDisplay
- 四人抢答器，用quartus编译过的，vhdl语言，说明详细，欢迎各位下载，-add display led
voter
- 用VHDL语言设计三人表决器 新建VHDL设计文件并保存 检查编译 波形仿真 -Design using VHDL language VHDL three new voting system for the design document and save it to check the compiler waveform simulation