资源列表
VHDL5
- 加法器 乘法器电路 除法器电路设计 键盘扫描电路设计 显示电路-Adder multiplier circuit divider circuit design keyboard scan circuit design show circuit, etc.
new_fifo
- 最新的testbench of FIFO ，使用Vmm，VCS，可以大致了解一下VMM的体系-the new fifo VMM testbench
fpga-control
- fpga 对采集的数据进行控制的相关verilog语言编程代码-fpga for collection of data related to control programming code verilog
verilog_example
- verilog的小程序集合，适合与初学者学习参考-The verilog small collection of programs suitable for beginners to learn reference
muxexamples
- Examples of different types of multiplexers
ALU_2016
- this files in Quartus 2 are ALU
anemometro
- anenometro digital creado en vhdl
UART-Transmitter
- UART transmitter using Verilog
ALU-and-Register-File
- ALU&Register Files(RF)之實現和其資料路徑的組合，包含了(1)ALU(2)Register File (RF)(3)Serial-in parallel-out register file(4)ALU + RF datapath-To learn the Verilog design for ALU and Register Files which are two main building blocks of a CPU.
Verilog-example-module
- code example. you are very professional
Test_Bench
- 波形发生器.经典双进程状态机.相应加法器的测试向量
agc
- 无线通信中接收侧自动增益控制模块的vhdl代码实现-Receive side of the AGC module vhdl code for wireless communications