资源列表
spi_verilog
- SPI protocol using veilog HDL
mt48lc8m16a2
- sdram的行为级模拟模块,可以模拟一个sdram,用于仿真对sdram的控制.-sdram behavioral simulation module can simulate a sdram. Simulation for the control of sdram.
RTL
- UART RTL测试程序，用于串口调试，红色飓风E16开发板使用-UART RTL test procedures for serial debugging
异步FIFO存储器的控制设计
- 异步FIFO控制器的设计 主要用于异步先进先出控制器的设计。 所用语言Verilog HDL.-asynchronous FIFO controller design for the main asynchronous FIFO controller design. The language used Verilog HDL.
v
- Verilog写的二分频电路代码，FPGA，实现将输入时钟信号的频率变成原来的1/2-Write Verilog code for the second divider circuit, FPGA, to achieve the frequency of the input clock signal into the original 1/2
clock
- 多功能数字钟：正常显示时分秒，设置调整时间，秒表，闹钟-Multifunctional digital clock: normal display, minutes and seconds, set to adjust the time, stopwatch, alarm clock
ANTITHEFTALARM1
- antitheft alarm in verilog
fifo_vhdl
- FIFO using vhdl and aslo configurable
code
- 基本元器件代码包括iv nd2 alu acc fa lfsr mux21 等-The basic components of the code include iv nd2 alu acc fa lfsr mux21 etc.
DAC_VHDL
- DAC VHDL code using SPI method
de2vga
- DE2 VGA控制代码，de2上控制VGA-DE2 VGA control code, de2 to control VGA
INC_DEC_GEN
- This an Generic Incrementer - Decrementer made wid flip-flops in VHDL-This is an Generic Incrementer - Decrementer made wid flip-flops in VHDL