资源列表
zj
- vhdl编程的，移位寄存器，八位，支持左移，右移-VHDL programming, shift register, 8, support the left, shifted to right
VHDL
- 多路分频及周期检测 端口映射示例程序-descr iption
MANCHESTER-ENCODING
- manchester encoding 波形-software for manchester encoding
smxsqddl
- 本实验只为了解教学系统中8位八段数码管显示模块的工作原理，设计标准扫描驱动电路模块.-this experiment only to understand the teaching system eight eight LED Display Module principle, design standards scanning drive circuit module.
fir
- FIR filter example for FPGA development
verilog-up-counter
- Verilog code for 4 bit Sync Up Counter
Elevator
- elevator contoller to control the movement of lift
period_cntr_avl
- Frequency measurement IP Core for ALTERA NIOS2
module-car
- this program describes the state machine function by verilog code
timer_rtl_source
- Timer verilog RTL code
clock
- 多功能数字钟 24小时计时 整点报时功能 闹钟设置功能 校时 复位等-Multi-function digital clock 24 hours to strike the alarm clock on the hour function when the reset function, etc
moore-FSM
- 该程序描述并且模拟和实现了了一个摩尔有限状态机的功能和作用-The program describes the simulation and the function and role of a mole finite state machine