资源列表
vga_gen
- VGA Control with VHDL in Altera DE0 Board
uart(Verilog)
- uart异步串口通信协议的源代码，用vhdl语言编写，并且有完整得测试文件
serial_div_uu_latest.tar
- serial divide with testbench
90477673uart(Verilog)
- uart通讯程序源代码，采用verilog编写-urat program（verilog)
Proteus-lcd
- This gives the function of proteus
_8-bit-booth-multiplier-pgm
- 8 BIT BOOTH MULTIPLIER
Electronic-clock
- 八位数码管显示电子时钟，显示年、月、日、星期，还有闹钟、整点报时的功能-Eight of the digital electronic clock, shows that the year, month, day, week, and alarm clock, the function of the time on the hour
Verilog_inout_
- verilog语言中inout端口的使用方法介绍-verilog language inout ports using the method described
intel_i8085_VHD
- This Intel s 8086 Series CORE VHDL example -This is Intel s 8086 Series CORE VHDL example
crc_verilog_xilinx
- crc校验，非常好用，是从Xilinx的IP演化来的
ddr_code
- 基于FPGA的DDR SDRAM控制器的VHDL硬件描述语言-FPGA-based DDR SDRAM controller VHDL hardware descr iption language
CANSHUHUA
- Verilog参数化的课件,有兴趣的可以来看下