资源列表
ceshixiangliang
- vhdl 测试向量含测试向量（Test Bench）和波形产生：VHDL实例---相应加法器的测试向量（test bench).txt-VHDL test vector containing test vector (Test Bench) and Waveform Generator : VHDL examples --- corresponding Adder test vector (test bench). Txt
32-crc32
- 32位数据输入并行算法Verilog HDL代码。-32 bits of data input and parallel algorithm Verilog HDL code
AHB_APB_leon_SYNvhdl.tar
- code regarding the ahb
B325_Assignment
- Assignment for a project
amba_sim_code
- AMBA Protocol implementation using VHDL
FIFOverilog
- 异步FIFO实现数据先入先出的存储方式基于verilog HDL语言-Asynchronous FIFO first-in, first-out data storage based on Verilog HDL language
frame_syn
- 通信系统中数据的传输以帧为单位，在FPGA中帧头检测是通信系统中的一部分，该程序实现了FPGA中帧头的检测。-Transmission of data in a communication system in units of frames, the frame header is detected in the FPGA part of the communication system, the realization of the frame header is detected in th
vhdl-examples
- 这是eda初学者可以借鉴的两个关于电子频率计的VHDL设计实例
mimasuo
- 4weimimasuo 可运行 可仿真 -aetgdffh tghj tjfgj fdg vbn t
fpga_fmsc
- 本代码在FPGA上实现了与STM32单片机的FSMC总线通信的时序代码，在ALTERA FPGA上得到验证。-The code on the FPGA to achieve with the STM32 microcontroller timing code FSMC bus communication is verified on ALTERA FPGA.
FIFOverilog
- 在FPGA进行数据的缓存，在跨时钟域应用较为广泛-Data cache, in the widely used cross-clock domain
jibengongtestbench
- testbench的基本写法，双口ram,双端口的编写 -The basic writing testbench, dual-port ram, dual-port the preparation of