资源列表
Rendering primitives
- Some 2D graphic rendering in VHDL: - Line - Draw a line - Circle - Draw circle - BitBLT - Draw a rectangle - Sine and cosinus lookup tables - Rotation - Rotate line
Bayer-filter
- Bayer filter-Bayer filter
counter
- 单片机程序 基于51单片机 计数器程序 适合初学者-Based on 51 single-chip microcontroller program counter program for beginners
Part-2-DWT-haar-using-VHDL
- Part 2 testbench for Discrete wavelet transfrom implementation in VHDL language Haar Filter
Div20PLL_vhd
- Div20PLL_vhd Div20PLL_vhd Div20PLL_vhd Div20PLL_vhd-Div20PLL_vhd Div20PLL_vhd Div20PLL_vhd Div20PLL_vhd Div20PLL_vhd Div20PLL_vhd
1-SDRAM
- 串行接口是最简单的一种通信方式，串口通信有两种方式，一种是同步串行，如SPI接口；另一种则是异步串行，即我们所说的UART。这个项目向大家展示了如何使用FPGA来模拟UART收发器。-uart fpga verilog
fir1
- system generator 构造fir滤波器模型结构-system generator constructed fir filter model structure
verilog-codes-for-booth2
- 由verilog编写的采用booth2编码的16*16乘法器-a 16*16 multiplier with booth2 coding by verilog
Multi-functionDigitalClock
- 可实现校时，仿电台报时，闹钟，报整点时数-The school can be realized when the fake radio timekeeping, alarm clock, reported that the number of hours the whole point of
vhdL
- VHDL多路选择器 （使用case语句）-VHDL multiplexer (using case statement)
count
- 计数器小程序，自己写的 代码短小但功能强大-Counter applet, write their own short but powerful code
FPGA1
- 用CPU配置Altera公司的FPGA1-CPU configuration with Altera Corporation FPGA1